/*
 * (C) Copyright 2007 by OpenMoko, Inc.
 * Author: Harald Welte <laforge@openmoko.org>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <video_fb.h>
#include <nand.h>
#include <pcf50606.h>
#include <s3c2440.h>

DECLARE_GLOBAL_DATA_PTR;

#define FCLK_SPEED 1

#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV	0xC3
#define M_PDIV	0x4
#define M_SDIV	0x1
#elif FCLK_SPEED==1
#if 0
#define M_MDIV	0x6e	/* Fout = 399.65MHz */
#define M_PDIV	0x3
#define M_SDIV	0x1
#else
#define M_MDIV	0x61	/* Fout = 296.35MHz due to wrong PLL capacitors */
#define M_PDIV	0x1
#define M_SDIV	0x2
#endif
#endif

#define USB_CLOCK 1

#if USB_CLOCK==0
#define U_M_MDIV	0xA1
#define U_M_PDIV	0x3
#define U_M_SDIV	0x1
#elif USB_CLOCK==1
#define U_M_MDIV	0x3c
#define U_M_PDIV	0x4
#define U_M_SDIV	0x2
#endif

static inline void delay (unsigned long loops)
{
	__asm__ volatile ("1:\n"
	  "subs %0, %1, #1\n"
	  "bne 1b":"=r" (loops):"0" (loops));
}

/*
 * Miscellaneous platform dependent initialisations
 */

int board_init (void)
{
	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

	/* to reduce PLL lock time, adjust the LOCKTIME register */
	clk_power->LOCKTIME = 0xFFFFFF;

	/* configure MPLL */
	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);

	/* some delay between MPLL and UPLL */
	delay (4000);

	/* configure UPLL */
	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);

	/* some delay between MPLL and UPLL */
	delay (8000);

	/* set up the I/O ports */
	gpio->GPACON = 0x005E0FFE;
	gpio->GPADAT = 0x0001C000;
	gpio->GPBCON = 0x00045542;
	gpio->GPBUP = 0x000007FF;
	gpio->GPCCON = 0xAAAA02A9;
	gpio->GPCUP = 0x0000FFFF;
	gpio->GPDCON = 0xAAAAAAAA;
	gpio->GPDUP = 0x0000FFFF;
	gpio->GPECON = 0xAAAAAAAA;
	gpio->GPEUP = 0x0000FFFF;
	gpio->GPFCON = 0x0000AAA9;
	gpio->GPFUP = 0x000000FF;
	gpio->GPGCON = 0x027D0316;
	gpio->GPGUP = 0x0000FFFF;
	gpio->GPHCON = 0x0014AAAA;
	gpio->GPHUP = 0x000007FF;
	gpio->GPJCON = 0x00000000;

	/* USB CHG enable */
	gpio->GPGDAT |= ( 1 << 11);
#if 0
	/* USB Device Part */
	/*GPGCON is reset for USB Device */
	gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
	gpio->GPGUP = gpio->GPGUP | ( 1 << 12);			/* Pull up disable */

	gpio->GPGDAT |= ( 1 << 12);
	gpio->GPGDAT &= ~( 1 << 12);
	udelay(20000);
	gpio->GPGDAT |= ( 1 << 12);
#endif

	/* arch number of SMDK2440-Board */
	gd->bd->bi_arch_number = MACH_TYPE_HXD8;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x30000100;

	icache_enable();
	dcache_enable();

	return 0;
}

void board_video_init(GraphicDevice *pGD)
{
	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();

	lcd->LCDCON1 = 0x0000057b;
	lcd->LCDCON2 = 0x0143c049;
	lcd->LCDCON3 = 0x0009df01;
	lcd->LCDCON4 = 0x00000028;
	lcd->LCDCON5 = 0x00000b08;

	lcd->TPAL = 0x01202020;

	//lcd->LCDCON5 |= (0x01 << 3);
}

int board_late_init(void)
{
	/* Initialize the Power Management Unit with a safe register set */
	pcf50606_init();

	return 0;
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	return 0;
}

u_int32_t get_board_rev(void)
{
	return 0x00000110;
}

/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
   "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
   images: 640*480*2*2 = 1228800 < 1245184. */

unsigned int dynpart_size[] = {
    CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3fd00000, 0 };
char *dynpart_names[] = {
    "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };

